1. Field of the Invention
The present invention relates generally to a semiconductor structure and method for fabricating the same, and more particularly to a multi-chip stack structure and method for fabricating the same.
2. Description of Related Art
Currently, multi-chip module (MCM) semiconductor packages have been developed to improve performance and capacity of single semiconductor packages, thereby meeting the demand for electronic products having smaller size and higher operation speed. Typically, two or more chips are disposed in a multi-chip module semiconductor package so as to reduce the entire structure volume of electronic products and improve electrical performance of the electronic products. In other words, by combining two or more chips in a single package structure, limit on the system operation speed is minimized, and in addition, the multi-chip package structure can reduce length of connecting circuit between the chips so as to reduce the signal delay and access time.
The multi-chip packages generally have a side-by-side structure, that is, two or more chips are side-by-side disposed to a common substrate, and electrically connected to the substrate by such as wire bonding. However, the side-by-side structure can lead to a high package cost and large package size since the area of the common substrate needs to increase as the number of the chips increases.
Accordingly, chip stack structures are proposed to overcome the above drawbacks. According to the difference designs of the chips, the wire bonding process of the chip stack structures can be slightly different. For example, if bonding pads of the chips are designed to be located at one side, such as flash memory chips or DRAMs (Dynamic Random Access Memory), the chips are stacked in a step-like manner for facilitating the wire bonding process. As shown in FIGS. 1A and 1B, wherein FIG. 1B is an upper view of FIG. 1A, a multi-chip stack substrate disclosed by U.S. Pat. No. 6,538,331 is shown. A plurality of memory chips is stacked on a chip carrier 10, wherein the first memory chip 11 is disposed on the chip carrier 10, the second memory chip 12 is stacked on the first memory chip 11 and offsets a certain distance from the first memory chip 11 such that the wire bonding process for bonding pads of the first memory chip 11 is not affected by the second memory chip 12. Further, a controller chip 13 is stacked on the second memory chip 12. The memory chips 11, 12 and the controller chip 13 are electrically connected to the chip carrier 10 through a plurality of bonding wires 15.
Further, in order to increase the memory capacity of memory cards, the number of the memory chips also needs to be increased. FIG. 2 shows a multi-chip stack structure disclosed by U.S. Pat. No. 6,621,155, wherein a plurality of memory chips 21, 22, 23, 24 is stacked on a chip carrier 20 in a step-like manner, and a controller chip 25 is further disposed on the memory chips 21, 22, 23, 24.
However, if more and more chips are stacked in the above-described way, the projecting area of the entire structure is continuously increased, when a certain number of the stack layers is reached, the memory chips will go out of the packageable range. Thus, the area of the chip carrier must be increased to finish the chip stack, which however increases the entire package volume and cannot meet requirement of small size and multifunctional electronic products.
Also, as planar size of a controller chip is far smaller than that of a memory chip, when the controller chip is electrically connected to a chip carrier through bonding wires, the bonding wires will definitely pass over the memory chips located below the controller chip, which can easily lead to contact of the bonding wires with the memory chips and even cause short circuit problems. Meanwhile, the wire bonding process becomes much more difficult.
On the other hand, if the controller chip is disposed to a region other than the region for disposing of the memory chips, the use area of the chip carrier is increased.
Referring to FIG. 3, Taiwan Patent No. I255492 discloses another multi-chip stack technique, wherein a plurality of memory chips 31, 32 is stacked on a chip carrier 30 in a step-like manner and electrically connected to the chip carrier 30 through bonding wires 36. Then, a buffer layer 37 is disposed on the memory chips 31, 32 and a plurality of memory chips 33, 34 is further disposed on the buffer layer 37 in a step-like manner. Thereafter, a controller chip 35 is disposed on the memory chips 33, 34. Thus, the number of the stacked chips is increased without going out of the packageable range.
However, the above-described method still cannot overcome the problem that the bonding wires of the controller chip contacting the memory chips on the lower side as well as the short circuit problem and wire bonding difficulty. Further, such a method requires long bonding wires and the wire arc is too high, which accordingly increases the process cost and can easily result in a wire sweep problem.
Meanwhile, the disposing of the buffer layer increases the process cost and steps, and also increases the height of the whole multi-chip structure, thereby making it difficult to be applied in fabricating thin type electronic devices such as Micro-SD cards.
Furthermore, in the above-described fabrication processes, as the controller chip is stacked on top of the memory chips, the height of the entire stack structure is adversely affected. In addition, too long bonding wires reduce electrical connection quality. If the number of the stack layers increases, delamination can easily occur on the interface.
Therefore, how to overcome the above-described drawbacks has become urgent.